1. Field of the Invention
The present invention relates to a method and apparatus for polishing a copper (Cu) layer and a method for forming a wiring structure using Cu, and more particularly to a method for polishing a Cu layer formed by an electro-plating and annealing process, a polishing apparatus that is suitable for performing the polishing method, and a method for forming a wiring structure using Cu.
2. Description of the Related Art
As information media, such as computers, continue to become more widely used, associated semiconductor technology must continue to advance. Functionally, semiconductor devices must operate at high speeds with ever-increasing storage capacity. Accordingly, semiconductor technology has evolved to continually improve the degree of integration, reliability and performance of semiconductor devices. For this reason, there are strict requirements for electric wiring techniques.
In a conventional electric wiring structure, aluminum is primarily used due to its lower contact resistance and relatively simple fabrication process. However, as semiconductor devices become more highly integrated, the aluminum wiring structure exhibits limitations such as a junction spike failure and electromigration. In addition, in order to improve the response speed of the semiconductor device, materials having a contact resistance lower than that of aluminum are needed.
Recently, a Cu wiring having a low resistance and superior electromigration characteristics have become widely used. However, Cu is rapidly diffused into silicon or other metal layers during processing. Thus, a conventional photolithography process is not suitable for Cu wiring. For this reason, a damascene process is generally used for forming Cu wiring. According to the conventional damascene process, a film is formed in order to bury a trench, and then a polishing process is carried out such that the film remains only in the trench, thereby forming a pattern. Therefore, the polishing process for the Cu metal layer is critical to the formation of Cu wiring in the damascene process. Accordingly, suitable process conditions and components (such as, a slurry, a polishing pad, and the like) are required for polishing the Cu metal layer.
FIGS. 1A and 1B are sectional views showing a conventional method for forming a Cu metal wiring.
Referring to FIG. 1A, an insulation layer 12 is formed on a silicon wafer 10. A trench 14 is formed at a predetermined portion on the insulation layer 12. The trench 14 eventually will become a passage for forming the Cu wiring. Then, a Cu metal layer 16 is formed to fill and bury the trench 14, for example through an electro-plating technique, and then the Cu is crystallized by a thermal heat treatment process. A method for removing voids from the Cu metal layer 16 by annealing the Cu metal layer 16 is disclosed in U.S. Pat. No. 6,121,141.
When annealing the Cu metal layer 16, a Cu oxide layer 18, such as CuO, or CuO2, is formed on a surface of the Cu metal layer 16 as a result of the reaction between Cu and oxygen. The resulting thickness of the Cu oxide layer 18 varies depending on the temperature and time of the annealing process. Generally, the Cu oxide layer 18 has a non-uniform thickness from 0 to several hundred angstroms (Å).
Referring to FIG. 1B, a Cu metal wiring 16a is formed by polishing an upper surface of the Cu metal layer 16 such that Cu remains only in the trench 14.
When performing the polishing process, the surface of the Cu metal layer 16 to be polished can be scratched, and the polishing uniformity can be lowered. That is, residue from the Cu oxide layer 18 formed on the surface of the Cu metal layer 16 and having a non-uniform thickness can operate as particles during polishing, such that scratches are created on the surface of the Cu metal layer 16. In addition, the polishing rate at each part of the silicon wafer varies depending on the corresponding thickness of the Cu oxide layer 18, so that the polishing uniformity is adversely affected.
Korean Patent Application No. 98-004144 (Korean Patent Laid-Open Publication No. 1998-071288) discloses a process for forming a Cu wiring. In this example, the Cu layer that is to be removed for forming the wiring is selectively oxidized by surface oxidation of the Cu layer. Then, the Cu oxide layer formed by the oxidation of the Cu layer is removed through the polishing or etching process, thereby forming the Cu wiring. However, it is very difficult to optimize the process condition such that the oxidation can be performed to an upper portion of the wiring, that is, to the very upper portion of the trench. If the Cu layer is not oxidized to the precise position, it is impossible to form the wiring through the etching or polishing process.